Pinouts

Introduction

Pinouts of some chips (all DIP) and connectors I use often. Chips are viewed from top. I'm not responsible for errors. Sources: GIICM, datasheets, Google.

7400 series chips

Gates

7400 – Quad 2-input NAND gates

Y = NOT (A AND B)

    +--\__/--+
 1A |1     14| VCC
 1B |2     13| 4B
 1Y |3     12| 4A
 2A |4     11| 4Y
 2B |5     10| 3B
 2Y |6      9| 3A
GND |7      8| 3Y
    +--------+

7402 – Quad 2-input NOR gates

Y = NOT (A OR B)

    +--\__/--+
 1Y |1     14| VCC
 1A |2     13| 4Y
 1B |3     12| 4B
 2Y |4     11| 4A
 2A |5     10| 3Y
 2B |6      9| 3B
GND |7      8| 3A
    +--------+

7404 – Hex inverters

Y = NOT A

    +--\__/--+
 1A |1     14| VCC
 1Y |2     13| 6A
 2A |3     12| 6Y
 2Y |4     11| 5A
 3A |5     10| 5Y
 3Y |6      9| 4A
GND |7      8| 4Y
    +--------+

7408 – Quad 2-input AND gates

Y = A AND B

    +--\__/--+
 1A |1     14| VCC
 1B |2     13| 4B
 1Y |3     12| 4A
 2A |4     11| 4Y
 2B |5     10| 3B
 2Y |6      9| 3A
GND |7      8| 3Y
    +--------+

7410 – Triple 3-input NAND gates

Y = NOT (A AND B AND C)

    +--\__/--+
 1A |1     14| VCC
 1B |2     13| 1C
 2A |3     12| 1Y
 2B |4     11| 3C
 2C |5     10| 3B
 2Y |6      9| 3A
GND |7      8| 3Y
    +--------+

7427 – Triple 3-input NOR gates

Y = NOT (A OR B OR C)

    +--\__/--+
 1A |1     14| VCC
 1B |2     13| 1C
 2A |3     12| 1Y
 2B |4     11| 3C
 2C |5     10| 3B
 2Y |6      9| 3A
GND |7      8| 3Y
    +--------+

7432 – Quad 2-input OR gates

Y = A OR B

    +--\__/--+
 1A |1     14| VCC
 1B |2     13| 4B
 1Y |3     12| 4A
 2A |4     11| 4Y
 2B |5     10| 3B
 2Y |6      9| 3A
GND |7      8| 3Y
    +--------+

7486 – Quad 2-input XOR gates

Y = A XOR B

    +--\__/--+
 1A |1     14| VCC
 1B |2     13| 4B
 1Y |3     12| 4A
 2A |4     11| 4Y
 2B |5     10| 3B
 2Y |6      9| 3A
GND |7      8| 3Y
    +--------+

Shift registers

7495 – 4-bit universal shift register

inputs: LD/SH, D, P, SHCLK, LDCLK
outputs: Q
parallel load (Q=P): LD/SH=H, LDCLK=↓
shift (D→Q0→…→Q3): LD/SH=L, SHCLK=↓

      +--\__/--+
    D |1     14| VCC
   P0 |2     13| Q0
   P1 |3     12| Q1
   P2 |4     11| Q2
   P3 |5     10| Q3
LD/SH |6      9| SHCLK
  GND |7      8| LDCLK
      +--------+

74164 – 8-bit serial-in parallel-out shift register

inputs: RST, D, E, CLK
outputs: Q
reset (Q=L): RST=L
shift (D&E→Q0→…→Q7): RST=H, CLK=↑

    +--\__/--+
  D |1     14| VCC
  E |2     13| Q7
 Q0 |3     12| Q6
 Q1 |4     11| Q5
 Q2 |5     10| Q4
 Q3 |6      9| RST
GND |7      8| CLK
    +--------+

74165 - 8-bit parallel-in serial-out shift register with complementary outputs

inputs: SH/LD, D, P, CLK1, CLK2
internal state: Q0…Q6
outputs: Q7, Q7
parallel load (Q=P): SH/LD=L
shift (D→Q0→…→Q7): SH/LD=H, CLK1=L, CLK2=↑

      +--\__/--+
SH/LD |1     16| VCC
 CLK1 |2     15| CLK2
   P4 |3     14| P3
   P5 |4     13| P2
   P6 |5     12| P1
   P7 |6     11| P0
   Q7 |7     10| D
  GND |8      9| Q7
      +--------+

74166 – 8-bit parallel-in serial-out shift register with reset

inputs: RST, SH/LD, D, P, CLK1, CLK2
internal state: Q0…Q6
outputs: Q7
clear (Q=L): RST=L
parallel load (Q=P): RST=H, SH/LD=L, CLK1=L, CLK2=↑
shift (D→Q0→…→Q7): RST=H, SH/LD=H, CLK1=L, CLK2=↑

     +--\__/--+
   D |1     16| VCC
  P0 |2     15| SH/LD
  P1 |3     14| P7
  P2 |4     13| Q7
  P3 |5     12| P6
CLK1 |6     11| P5
CLK2 |7     10| P4
 GND |8      9| RST
     +--------+

D flip-flops

7474 – Dual D flip-flop with set and reset

inputs: RST, SET, D, CLK
outputs: Q, Q
if RST=L and SET=H: Q=L
if RST=H and SET=L: Q=H
if RST=H and SET=H and CLK=↑: Q=D

     +--\__/--+
1RST |1     14| VCC
  1D |2     13| 2RST
1CLK |3     12| 2D
1SET |4     11| 2CLK
  1Q |5     10| 2SET
  1Q |6      9| 2Q
 GND |7      8| 2Q
     +--------+

74173 – 4-bit 3-state D flip-flop

inputs: RST, CLKEN, CLK, D, OE
outputs: Q
if RST=H: internal data=L
if RST=L and CLKEN1=L and CLKEN2=L and CLK=↑: internal data=D
if OE1=H or OE2=H: Q=Z
if OE1=L and OE2=L: Q=internal data

    +--\__/--+
OE1 |1     16| VCC
OE2 |2     15| RST
 Q0 |3     14| D0
 Q1 |4     13| D1
 Q2 |5     12| D2
 Q3 |6     11| D3
CLK |7     10| CLKEN1
GND |8      9| CLKEN2
    +--------+

74174 – 6-bit D flip-flop with clear

inputs: RST, D, CLK
outputs: Q
if RST=L: Q=L
if RST=H and CLK=↑: Q=D

    +--\__/--+
RST |1     16| VCC
 Q0 |2     15| Q5
 D0 |3     14| D5
 D1 |4     13| D4
 Q1 |5     12| Q4
 D2 |6     11| D3
 Q2 |7     10| Q3
GND |8      9| CLK
    +--------+

74273 – Octal D flip-flop with clear

inputs: RST, D, CLK
outputs: Q
if RST=L: Q=L
if RST=H and CLK=↑: Q=D

    +--\__/--+
RST |1     20| VCC
 1Q |2     19| 8Q
 1D |3     18| 8D
 2D |4     17| 7D
 2Q |5     16| 7Q
 3Q |6     15| 6Q
 3D |7     14| 6D
 4D |8     13| 5D
 4Q |9     12| 5Q
GND |10    11| CLK
    +--------+

74374 – Octal D flip-flop with 3-state output

inputs: OE, D, CLK
outputs: Q
if OE=H: Q=Z
if OE=L and CLK=↑: Q=D

    +--\__/--+
 OE |1     20| VCC
 Q1 |2     19| Q8
 D1 |3     18| D8
 D2 |4     17| D7
 Q2 |5     16| Q7
 Q3 |6     15| Q6
 D3 |7     14| D6
 D4 |8     13| D5
 Q4 |9     12| Q5
GND |10    11| CLK
    +--------+

Buffers/transceivers

74125 – Quad 3-state noninverting buffer with active low enables

inputs: OE, A
outputs: Y
if OE=H: Y=Z
if OE=L: Y=A

    +--\__/--+
1OE |1     14| VCC
 1A |2     13| 4OE
 1Y |3     12| 4A
2OE |4     11| 4Y
 2A |5     10| 3OE
 2Y |6      9| 3A
GND |7      8| 3Y
    +--------+

74245 – 8-bit 3-state noninverting bus transceiver

inputs: EN, DIR
bidirectional: A, B
if EN=H: A,B = Z
if EN=L, DIR=L: A=B
if EN=L, DIR=H: B=A

    +--\__/--+
DIR |1     20| VCC
 A1 |2     19| EN
 A2 |3     18| B1
 A3 |4     17| B2
 A4 |5     16| B3
 A5 |6     15| B4
 A6 |7     14| B5
 A7 |8     13| B6
 A8 |9     12| B7
GND |10    11| B8
    +--------+

Multiplexers

74151 – 8-to-1 data selector/multiplexer with complementary outputs

inputs: EN, S (S2=MSB), D
outputs: Y
if EN=H: Y=L
if EN=L: Y = D specified by S

    +--\__/--+
 D3 |1     16| VCC
 D2 |2     15| D4
 D1 |3     14| D5
 D0 |4     13| D6
  Y |5     12| D7
  Y |6     11| S0
 EN |7     10| S1
GND |8      9| S2
    +--------+

74153 – dual 4-to-1 data selector/multiplexer with separate enables

inputs: EN, S (S1=MSB), A
outputs: Y
if EN=H: Y=L
if EN=L: Y = A specified by S

    +--\__/--+
1EN |1     16| VCC
 S1 |2     15| 2EN
1A3 |3     14| S0
1A2 |4     13| 2A3
1A1 |5     12| 2A2
1A0 |6     11| 2A1
 1Y |7     10| 2A0
GND |8      9| 2Y
    +--------+

74157 – quad 2-to-1 data selector/multiplexer

inputs: EN, S, A
outputs: Y
if EN=H: Y=L
if EN=L: Y = A specified by S

    +--\__/--+
  S |1     16| VCC
1A0 |2     15| EN
1A1 |3     14| 4A0
 1Y |4     13| 4A1
2A0 |5     12| 4Y
2A1 |6     11| 3A0
 2Y |7     10| 3A1
GND |8      9| 3Y
    +--------+

74158 – quad 2-to-1 data selector/multiplexer, inverting

inputs: EN, S, A
outputs: Y
if EN=H: Y=H
if EN=L and S=L: Y = NOT A0
if EN=L and S=H: Y = NOT A1

    +--\__/--+
  S |1     16| VCC
1A0 |2     15| EN
1A1 |3     14| 4A0
 1Y |4     13| 4A1
2A0 |5     12| 4Y
2A1 |6     11| 3A0
 2Y |7     10| 3A1
GND |8      9| 3Y
    +--------+

74257 – quad 2-to-1 data selector/multiplexer, 3-state

inputs: EN, S, A
outputs: Y
if EN=H: Y=Z
if EN=L and S=L: Y=A0
if EN=L and S=H: Y=A1

    +--\__/--+
  S |1     16| VCC
1A0 |2     15| EN
1A1 |3     14| 4A0
 1Y |4     13| 4A1
2A0 |5     12| 4Y
2A1 |6     11| 3A0
 2Y |7     10| 3A1
GND |8      9| 3Y
    +--------+

Demultiplexers

7442 – 1-of-10 decoder/demultiplexer, inverting

inputs: S (S3=MSB)
outputs: Y
if S≤9: Y specified by S will be L and other Y will be H
if S>9: Y = H

    +--\__/--+
 Y0 |1     16| VCC
 Y1 |2     15| S0
 Y2 |3     14| S1
 Y3 |4     13| S2
 Y4 |5     12| S3
 Y5 |6     11| Y9
 Y6 |7     10| Y8
GND |8      9| Y7
    +--------+

74138 – 1-of-8 decoder/demultiplexer, inverting

inputs: EN, S (S2=MSB)
outputs: Y
if EN1=L or EN2=H or EN3=H: Y=H
if EN1=H and EN2=L and EN3=L: Y specified by S will be L and other Y will be H

    +--\__/--+
 S0 |1     16| VCC
 S1 |2     15| Y0
 S2 |3     14| Y1
EN3 |4     13| Y2
EN2 |5     12| Y3
EN1 |6     11| Y4
 Y7 |7     10| Y5
GND |8      9| Y6
    +--------+

74139 – dual 1-of-4 decoder/demultiplexer, inverting

inputs: EN, S (S1=MSB)
outputs: Y
if EN=H: Y=H
if EN=L: Y specified by S will be L and other Y will be H

    +--\__/--+
1EN |1     16| VCC
1S0 |2     15| 2EN
1S1 |3     14| 2S0
1Y0 |4     13| 2S1
1Y1 |5     12| 2Y0
1Y2 |6     11| 2Y1
1Y3 |7     10| 2Y2
GND |8      9| 2Y3
    +--------+

Other

74283 – 4-bit binary full adder with fast carry

inputs: A (A4=MSB), B (B4=MSB), CIN
outputs: S (S4=MSB), COUT
S, COUT = A+B+CIN (S1 = A1 XOR B1 XOR CIN, etc.)

    +--\__/--+
 S2 |1     16| VCC
 B2 |2     15| B3
 A2 |3     14| A3
 S1 |4     13| S3
 A1 |5     12| A4
 B1 |6     11| B4
CIN |7     10| S4
GND |8      9| COUT
    +--------+

74393 – Dual 4-bit asynchronous binary counters with reset

inputs: RST, CLK
outputs: Q (Q3=MSB)

     +--\__/--+
1CLK |1     14| VCC
1RST |2     13| 2CLK
 1Q0 |3     12| 2RST
 1Q1 |4     11| 2Q0
 1Q2 |5     10| 2Q1
 1Q3 |6      9| 2Q2
 GND |7      8| 2Q3
      +--------+

Memory chips

6116 – 2k×8-bit static RAM

inputs: CE, OE, WE, A
bidirectional: D

    +--\__/--+
 A7 |1     24| VCC
 A6 |2     23| A8
 A5 |3     22| A9
 A4 |4     21| WE
 A3 |5     20| OE
 A2 |6     19| A10
 A1 |7     18| CE
 A0 |8     17| D7
 D0 |9     16| D6
 D1 |10    15| D5
 D2 |11    14| D4
GND |12    13| D3
    +--------+

6264 – 8k×8-bit static RAM

inputs: CE1, CE2, OE, WE, A
bidirectional: D

    +--\__/--+
 NC |1     28| VCC
A12 |2     27| WE
 A7 |3     26| CE2
 A6 |4     25| A8
 A5 |5     24| A9
 A4 |6     23| A11
 A3 |7     22| OE
 A2 |8     21| A10
 A1 |9     20| CE1
 A0 |10    19| D7
 D0 |11    18| D6
 D1 |12    17| D5
 D2 |13    16| D4
GND |14    15| D3
    +--------+

62256 – 32k×8-bit static RAM

inputs: CE, OE, WE, A
bidirectional: D

    +--\__/--+
A14 |1     28| VCC
A12 |2     27| WE
 A7 |3     26| A13
 A6 |4     25| A8
 A5 |5     24| A9
 A4 |6     23| A11
 A3 |7     22| OE
 A2 |8     21| A10
 A1 |9     20| CE
 A0 |10    19| D7
 D0 |11    18| D6
 D1 |12    17| D5
 D2 |13    16| D4
GND |14    15| D3
    +--------+

628128 – 128k×8-bit static RAM

inputs: CE1, CE2, OE, WE, A
bidirectional: D

    +--\__/--+
 NC |1     32| VCC
A16 |2     31| A15
A14 |3     30| CE2
A12 |4     29| WE
 A7 |5     28| A13
 A6 |6     27| A8
 A5 |7     26| A9
 A4 |8     25| A11
 A3 |9     24| OE
 A2 |10    23| A10
 A1 |11    22| CE1
 A0 |12    21| D7
 D0 |13    20| D6
 D1 |14    19| D5
 D2 |15    18| D4
GND |16    17| D3
    +--------+

27512 – 64k×8-bit EPROM

    +--\__/--+
A15 |1     28| VDD
A12 |2     27| A14
 A7 |3     26| A13
 A6 |4     25| A8
 A5 |5     24| A9
 A4 |6     23| A11
 A3 |7     22| OE
 A2 |8     21| A10
 A1 |9     20| CE
 A0 |10    19| D7
 D0 |11    18| D6
 D1 |12    17| D5
 D2 |13    16| D4
GND |14    15| D3
    +--------+

39SF512 – 512k×8-bit flash

    +--\__/--+
 NC |1     32| VDD
 NC |2     31| WE
A15 |3     30| NC
A12 |4     29| A14
 A7 |5     28| A13
 A6 |6     27| A8
 A5 |7     26| A9
 A4 |8     25| A11
 A3 |9     24| OE
 A2 |10    23| A10
 A1 |11    22| CE
 A0 |12    21| D7
 D0 |13    20| D6
 D1 |14    19| D5
 D2 |15    18| D4
GND |16    17| D3
    +--------+

39SF010 – 1024k×8-bit flash

    +--\__/--+
 NC |1     32| VDD
A16 |2     31| WE
A15 |3     30| NC
A12 |4     29| A14
 A7 |5     28| A13
 A6 |6     27| A8
 A5 |7     26| A9
 A4 |8     25| A11
 A3 |9     24| OE
 A2 |10    23| A10
 A1 |11    22| CE
 A0 |12    21| D7
 D0 |13    20| D6
 D1 |14    19| D5
 D2 |15    18| D4
GND |16    17| D3
    +--------+

Misc chips

Zilog Z80

inputs: WAIT, INT, NMI, RST, BUSRQ, CLK
bidirectional: D
outputs: A, M1, MREQ, IORQ, RD, WR, RFSH, HALT, BUSAK

     +--\__/--+
 A11 |1     40| A10
 A12 |2     39| A9
 A13 |3     38| A8
 A14 |4     37| A7
 A15 |5     36| A6
 CLK |6     35| A5
  D4 |7     34| A4
  D3 |8     33| A3
  D5 |9     32| A2
  D6 |10    31| A1
 VCC |11    30| A0
  D2 |12    29| GND
  D7 |13    28| RFSH
  D0 |14    27| M1
  D1 |15    26| RST
 INT |16    25| BUSRQ
 NMI |17    24| WAIT
HALT |18    23| BUSAK
MREQ |19    22| WR
IORQ |20    21| RD
     +--------+

Motorola MC6850

ACIA (Asynchronous Communications Interface Adapter)
pins:
- input – chip select and read/write control: E, CS0, CS1, CS2, R/W, RS (register select)
- input – other: TXCLK, RXCLK, RXDAT, DCD (data carrier detect), CTS (clear to send)
- bidirectional: D
- output: TXDAT, IRQ, RTS (request to send)
registers:
- status (read): R/W=H, RS=L
- receive data: R/W=H, RS=H
- control (write): R/W=L, RS=L, E=↓
- transmit data: R/W=L, RS=H, E=↓

      +--\__/--+
  GND |1     24| CTS
RXDAT |2     23| DCD
RXCLK |3     22| D0
TXCLK |4     21| D1
  RTS |5     20| D2
TXDAT |6     19| D3
  IRQ |7     18| D4
  CS0 |8     17| D5
  CS2 |9     16| D6
  CS1 |10    15| D7
   RS |11    14| E
  VCC |12    13| R/W
      +--------+

Misc connectors

Raspberry Pi GPIO

20×2-pin male header on PCB
even-numbered pins are closest to the edge of the PCB

            +------+
        3V3 |1    2| 5V
   SDA/GPIO |3    4| 5V
   SCL/GPIO |5    6| GND
GPCLK0/GPIO |7    8| GPIO/TXD
        GND |9   10| GPIO/RXD
       GPIO |11  12| GPIO/PCM_CLK
       GPIO |13  14| GND
       GPIO |15  16| GPIO
        3V3 |17  18| GPIO
  MOSI/GPIO |19  20| GND
  MISO/GPIO |21  22| GPIO
  SCLK/GPIO |23  24| GPIO/CE0
        GND |25  26| GPIO/CE1
 ID_SD/GPIO |27  28| GPIO/ID_SC
       GPIO |29  30| GND
       GPIO |31  32| GPIO/PWM0
  PWM1/GPIO |33  34| GND
PCM_FS/GPIO |35  36| GPIO
       GPIO |37  38| GPIO/PCM_DIN
        GND |39  40| GPIO/PCM_DOUT
            +------+

RC2014 bus

40-pin 0.1″ in-line female pin header on backplane

 1  A15
 2  A14
 3  A13
 4  A12
 5  A11
 6  A10
 7  A9
 8  A8
 9  A7
10  A6
11  A5
12  A4
13  A3
14  A2
15  A1
16  A0
17  GND
18  5V
19  M1
20  RST
21  CLK
22  INT
23  MREQ
24  WR
25  RD
26  IORQ
27  D0
28  D1
29  D2
30  D3
31  D4
32  D5
33  D6
34  D7
35  TX
36  RX
37  NC
38  NC
39  NC
40  NC

HD44780 LCD module

16 pins in-line
use DB7…DB4 for 4-bit mode
VO=contrast
see also RC2014 devices I've built!

 1  VSS  ground
 2  VDD  supply voltage for logic (5V)
 3  VO   operating voltage for LCD (variable)
 4  RS   H=data, L=instruction
 5  R/W  H=read, L=write
 6  E    chip enable
 7  DB0  data bus line
 8  DB1  data bus line
 9  DB2  data bus line
10  DB3  data bus line
11  DB4  data bus line
12  DB5  data bus line
13  DB6  data bus line
14  DB7  data bus line
15  A    LED+
16  K    LED-