My fantasy CPU

Introduction

I have designed an instruction set for an imaginary 8-bit CPU. It is a superset of the 65C02. The 65C02 has 64 mnemonics, 15 addressing modes and 178 combinations of mnemonic and addressing mode. My CPU has the same addressing modes but 91 mnemonics and 251 combinations of mnemonic and addressing mode. My additions are highlighted like this or like this.

Instructions with implied addressing only

All 29 mnemonics from the 65C02: BRK, CLC, CLD, CLI, CLV, DEX, DEY, INX, INY, NOP, PHA, PHP, PHX, PHY, PLA, PLP, PLX, PLY, RTI, RTS, SEC, SED, SEI, TAX, TAY, TSX, TXA, TXS, TYA.

23 new mnemonics; they operate on the A, X and Y registers and flags only:

Mnemonic Description In other CPUs
SEV Set overflow flag.
CPC Complement (invert) carry flag. Z80 CCF
TXY Transfer (copy) X to Y. 65816 TXY
TYX Transfer (copy) Y to X. 65816 TYX
SAX Swap A and X. HuC6280 SAX
SAY Swap A and Y. HuC6280 SAY
SXY Swap X and Y. HuC6280 SXY
ANX AND A with X. Like AND but the operand is X.
ANY AND A with Y. Like AND but the operand is Y.
EOX Exclusive-OR A with X. Like EOR but the operand is X.
EOY Exclusive-OR A with Y. Like EOR but the operand is Y.
ORX OR A with X. Like ORA but the operand is X.
ORY OR A with Y. Like ORA but the operand is Y.
ADX Add X to A with carry. Like ADC but the operand is X.
ADY Add Y to A with carry. Like ADC but the operand is Y.
SBX Subtract X from A with carry. Like SBC but the operand is X.
SBY Subtract Y from A with carry. Like SBC but the operand is Y.
CMX Compare A with X. Like CMP but the operand is X.
CMY Compare A with Y. Like CMP but the operand is Y.
CXA Compare X with A. Like CPX but the operand is A.
CXY Compare X with Y. Like CPX but the operand is Y.
CYA Compare Y with A. Like CPY but the operand is A.
CYX Compare Y with X. Like CPY but the operand is X.

Instructions with relative addressing only

All 9 mnemonics from the 65C02: BCC, BCS, BEQ, BMI, BNE, BPL, BRA, BVC, BVS.

No new mnemonics.

Instructions with multiple addressing modes

All 26 mnemonics from the 65C02: ADC, AND, ASL, BIT, CMP, CPX, CPY, DEC, EOR, INC, JMP, JSR, LDA, LDX, LDY, LSR, ORA, ROL, ROR, SBC, STA, STX, STY, STZ, TRB, TSB.

4 new mnemonics:

Mnemonic Description Example In other CPUs
ASR Arithmetic shift right memory or A. ASR A is like CMP #$80 & ROR A. Z80 SRA, x86 SAR
REL Rotate memory or A left in an 8-bit fashion. REL A is like CMP #$80 & ROL A. Z80 RLC, x86 ROL
RER Rotate memory or A right in an 8-bit fashion. RER A is like PHA & LSR A & PLA & ROR A. Z80 RRC, x86 ROR
CPL Complement (invert) memory or A. CPL A is like EOR #$FF. Z80 CPL, x86 NOT

All 140 combinations of mnemonic and addressing mode from the 65C02, 26 new ones for the old mnemonics to make the instruction set more orthogonal, and 24 new ones for the new mnemonics:

Mnemonic Addressing mode
#imm A abs zp abs,x zp,x abs,y zp,y (zp) (zp,x) (zp),y (abs) (abs,x)
LDA • • • • • • • • •
STA • • • • • • • •
AND • • • • • • • • •
ORA • • • • • • • • •
EOR • • • • • • • • •
SBC • • • • • • • • •
CMP • • • • • • • • •
ADC • • • • • • • • •
ASL • • • • • •
ASR • • • • • •
LSR • • • • • •
REL • • • • • •
RER • • • • • •
ROL • • • • • •
ROR • • • • • •
CPL • • • • • •
DEC • • • • • •
INC • • • • • •
LDX • • • • •
STX • • • •
CPX • • • • •
LDY • • • • •
STY • • • •
CPY • • • • •
BIT • • • • • •
STZ • • • • •
TRB • • • • •
TSB • • • • •
JMP • • • • •
JSR • • • • •

Instructions that didn't make the cut

See also Synthetic instructions on NESDev Wiki.

Implied addressing

Mnemonic Description Approximate equivalent In other CPUs
CLA clear A LDA #0 HuC6280 CLA
CLX clear X LDX #0 HuC6280 CLX
CLY clear Y LDY #0 HuC6280 CLY
ADZ add carry to A ADC #0
SBZ subtract (1 − carry) from A SBC #0
FLX set N and Z flags (not C) according to X INX & DEX
FLY set N and Z flags (not C) according to Y INY & DEY
TAS transfer (copy) A to stack pointer PHX & TAX & TXS & PLX 65816 TCS
TSA transfer (copy) stack pointer to A PHX & TSX & TXA & PLX 65816 TSC
TAP transfer (copy) A to processor status PHA & PLP
TPA transfer (copy) processor status to A PHP & PLA
RCC, RCS, REQ, RMI, RNE, RPL, RVC, RVS return from subroutine if condition RCC is like BCS skip & RTS & skip: Z80 RET with condition

Non-implied addressing

Mnemonic Description Approximate equivalent In other CPUs
ADD add memory or immediate to A without carry ADD operand is like CLC & ADC operand Z80, x86 ADD
SUB subtract memory or immediate from A without carry SUB operand is like SEC & SBC operand Z80, x86 SUB
NEG negate memory or A in two's complement NEG A is like EOR #$FF & INC A Z80, x86 NEG
PSH push memory or immediate to stack PSH operand is like LDA operand & PHA but A unaffected x86 PUSH
PUL pull (pop) from stack to memory PUL memory is like PLA & STA memory but A unaffected x86 POP
BSR branch to subroutine BSR sub is like JSR sub but with PC-relative addressing HuC6280 BSR
JCC, JCS, JEQ, JMI, JNE, JPL, JVC, JVS jump if condition (see RCC etc. above) JCC target is like BCS skip & JMP target & skip: Z80 JP with condition
SCC, SCS, SEQ, SMI, SNE, SPL, SVC, SVS jump to subroutine if condition (see RCC etc. above) SCC sub is like BCS skip & JSR sub & skip: Z80 CALL with condition
TEB exclusive-OR bits in memory according to A TEB memory is like PHA & EOR memory & STA memory & PLA