My fantasy CPU

Introduction

I have designed an instruction set for an imaginary 8-bit CPU. It is a superset of the 65C02. The 65C02 has 64 mnemonics, 15 addressing modes and 178 combinations of mnemonic and addressing mode. My CPU has the same addressing modes but 91 mnemonics and 251 combinations of mnemonic and addressing mode. My additions are highlighted like this or like this.

Instructions with implied addressing only

All 29 mnemonics from the 65C02: BRK, CLC, CLD, CLI, CLV, DEX, DEY, INX, INY, NOP, PHA, PHP, PHX, PHY, PLA, PLP, PLX, PLY, RTI, RTS, SEC, SED, SEI, TAX, TAY, TSX, TXA, TXS, TYA.

23 new mnemonics; they operate on the A, X and Y registers and flags only:

Mnemonic Description In other CPUs
SEV Set overflow flag.
CCF Complement (invert) carry flag. Z80 CCF
TXY Copy X to Y. 65816 TXY
TYX Copy Y to X. 65816 TYX
SAX Swap A and X. HuC6280 SAX
SAY Swap A and Y. HuC6280 SAY
SXY Swap X and Y. HuC6280 SXY
ANX AND A with X. Like AND but the operand is X.
ANY AND A with Y. Like AND but the operand is Y.
EOX Exclusive-OR A with X. Like EOR but the operand is X.
EOY Exclusive-OR A with Y. Like EOR but the operand is Y.
ORX OR A with X. Like ORA but the operand is X.
ORY OR A with Y. Like ORA but the operand is Y.
ADX Add X to A with carry. Like ADC but the operand is X.
ADY Add Y to A with carry. Like ADC but the operand is Y.
SBX Subtract X from A with carry. Like SBC but the operand is X.
SBY Subtract Y from A with carry. Like SBC but the operand is Y.
CMX Compare A with X. Like CMP but the operand is X.
CMY Compare A with Y. Like CMP but the operand is Y.
CXA Compare X with A. Like CPX but the operand is A.
CXY Compare X with Y. Like CPX but the operand is Y.
CYA Compare Y with A. Like CPY but the operand is A.
CYX Compare Y with X. Like CPY but the operand is X.

Instructions with relative addressing only

All 9 mnemonics from the 65C02: BCC, BCS, BEQ, BMI, BNE, BPL, BRA, BVC, BVS.

No new mnemonics.

Instructions with multiple addressing modes

All 26 mnemonics from the 65C02: ADC, AND, ASL, BIT, CMP, CPX, CPY, DEC, EOR, INC, JMP, JSR, LDA, LDX, LDY, LSR, ORA, ROL, ROR, SBC, STA, STX, STY, STZ, TRB, TSB.

4 new mnemonics:

Mnemonic Description In other CPUs
ASR Arithmetic shift right memory or A. ASR A is equivalent to CMP #$80 & ROR A. Z80 SRA, x86 SAR
REL Rotate memory or A left in an 8-bit fashion. REL A is equivalent to CMP #$80 & ROL A. Z80 RLC, x86 ROL
RER Rotate memory or A right in an 8-bit fashion. RER A is equivalent to PHA & LSR A & PLA & ROR A. Z80 RRC, x86 ROR
CPL Complement (invert) memory or A. Z80 CPL, x86 NOT

All 140 combinations of mnemonic and addressing mode from the 65C02, 26 new ones for the old mnemonics to make the instruction set more orthogonal, and 24 new ones for the new mnemonics:

Mnemonic Addressing mode
#imm A abs zp abs,x zp,x abs,y zp,y (zp) (zp,x) (zp),y (abs) (abs,x)
LDA • • • • • • • • •
STA • • • • • • • •
AND • • • • • • • • •
ORA • • • • • • • • •
EOR • • • • • • • • •
SBC • • • • • • • • •
CMP • • • • • • • • •
ADC • • • • • • • • •
ASL • • • • • •
ASR • • • • • •
LSR • • • • • •
REL • • • • • •
RER • • • • • •
ROL • • • • • •
ROR • • • • • •
CPL • • • • • •
DEC • • • • • •
INC • • • • • •
LDX • • • • •
STX • • • •
CPX • • • • •
LDY • • • • •
STY • • • •
CPY • • • • •
BIT • • • • • •
STZ • • • • •
TRB • • • • •
TSB • • • • •
JMP • • • • •
JSR • • • • •

Possible future instructions

See also Synthetic instructions on NESDev Wiki.

Implied addressing

Mnemonic Description In other CPUs
CLA Clear A. HuC6280 CLA
CLX Clear X. HuC6280 CLX
CLY Clear Y. HuC6280 CLY
ADZ Like ADC #0.
SBZ Like SBC #0.
FLA Set N and Z flags according to A. Like CMP #0 but doesn't affect carry.
FLX Set N and Z flags according to X. Like CPX #0 but doesn't affect carry.
FLY Set N and Z flags according to Y. Like CPY #0 but doesn't affect carry.
TAS Transfer A to stack pointer. 65816 TCS
TSA Transfer stack pointer to A. 65816 TSC
TAP Transfer A to processor status.
TPA Transfer processor status to A.
Rcc RTS if condition cc; e.g. REQ, RNE. Z80 RET c
DAX Decrement 16-bit register pair A & X.
IAX Increment 16-bit register pair A & X.
DAY Decrement 16-bit register pair A & Y.
IAY Increment 16-bit register pair A & Y.
DXY Decrement 16-bit register pair X & Y.
IXY Increment 16-bit register pair X & Y.

Non-implied addressing

Mnemonic Description In other CPUs
ADD Like CLC & ADC. Z80, x86 ADD
SUB Like SEC & SBC. Z80, x86 SUB
NEG Negate memory or A in two's complement. Z80, x86 NEG
PSH Push memory or immediate to stack. x86 PUSH
PUL Pull from stack to memory. x86 POP
BSR BRA to subroutine. HuC6280 BSR
Jcc JMP if condition cc; e.g. JEQ, JNE, … Z80 JP c, x
Scc JSR if condition cc; e.g. SEQ, SNE, … Z80 CALL c, x
TEB Exclusive-OR bits in memory according to A.