My fantasy CPU

Introduction

I have designed an instruction set for an imaginary 8-bit CPU. It is a superset of the 65C02. The 65C02 has 64 mnemonics, 15 addressing modes and 178 combinations of mnemonic and addressing mode. My CPU has the same addressing modes but 88 mnemonics and 248 combinations of mnemonic and addressing mode. My additions are highlighted like this or like this.

Instructions with implied addressing only

All 29 mnemonics from the 65C02: BRK, CLC, CLD, CLI, CLV, DEX, DEY, INX, INY, NOP, PHA, PHP, PHX, PHY, PLA, PLP, PLX, PLY, RTI, RTS, SEC, SED, SEI, TAX, TAY, TSX, TXA, TXS, TYA.

20 new mnemonics; they operate on the A, X and Y registers and flags only:

Mnemonic Description In other CPUs
SEV Set overflow flag.
CPC Complement (invert) carry flag. Z80 CCF
TXY Transfer (copy) X to Y. 65816 TXY
TYX Transfer (copy) Y to X. 65816 TYX
ANX AND A with X. Like AND but the operand is X.
ANY AND A with Y. Like AND but the operand is Y.
EOX Exclusive-OR A with X. Like EOR but the operand is X.
EOY Exclusive-OR A with Y. Like EOR but the operand is Y.
ORX OR A with X. Like ORA but the operand is X.
ORY OR A with Y. Like ORA but the operand is Y.
ADX Add X to A with carry. Like ADC but the operand is X.
ADY Add Y to A with carry. Like ADC but the operand is Y.
SBX Subtract X from A with carry. Like SBC but the operand is X.
SBY Subtract Y from A with carry. Like SBC but the operand is Y.
CMX Compare A with X. Like CMP but the operand is X.
CMY Compare A with Y. Like CMP but the operand is Y.
CXA Compare X with A. Like CPX but the operand is A.
CXY Compare X with Y. Like CPX but the operand is Y.
CYA Compare Y with A. Like CPY but the operand is A.
CYX Compare Y with X. Like CPY but the operand is X.

Instructions with relative addressing only

All 9 mnemonics from the 65C02: BCC, BCS, BEQ, BMI, BNE, BPL, BRA, BVC, BVS.

No new mnemonics.

Instructions with multiple addressing modes

All 26 mnemonics from the 65C02: ADC, AND, ASL, BIT, CMP, CPX, CPY, DEC, EOR, INC, JMP, JSR, LDA, LDX, LDY, LSR, ORA, ROL, ROR, SBC, STA, STX, STY, STZ, TRB, TSB.

4 new mnemonics:

Mnemonic Description Approximate equivalent In other CPUs
ASR Arithmetic shift right memory or A. ASR A is like CMP #$80 & ROR A. Z80 SRA, x86 SAR
REL Rotate memory or A left in an 8-bit fashion. REL A is like CMP #$80 & ROL A. Z80 RLC, x86 ROL
RER Rotate memory or A right in an 8-bit fashion. RER A is like PHA & LSR A & PLA & ROR A. Z80 RRC, x86 ROR
CPL Complement (invert) memory or A. CPL A is like EOR #$FF. Z80 CPL, x86 NOT

All 140 combinations of mnemonic and addressing mode from the 65C02, 26 new ones for the old mnemonics to make the instruction set more orthogonal, and 24 new ones for the new mnemonics:

Mnemonic Addressing mode
#imm A abs zp abs,x zp,x abs,y zp,y (zp) (zp,x) (zp),y (abs) (abs,x)
LDA old old old old old old old old old
STA old old old old old old old old
AND old old old old old old old old old
ORA old old old old old old old old old
EOR old old old old old old old old old
SBC old old old old old old old old old
CMP old old old old old old old old old
ADC old old old old old old old old old
ASL old old old old old new
ASR (new) new new new new new new
LSR old old old old old new
REL (new) new new new new new new
RER (new) new new new new new new
ROL old old old old old new
ROR old old old old old new
CPL (new) new new new new new new
DEC old old old old old new
INC old old old old old new
LDX old old old old old
STX old old new old
CPX old old old new new
LDY old old old old old
STY old old new old
CPY old old old new new
BIT old old old old old new
STZ old old old old new
TRB old old new new new
TSB old old new new new
JMP old new new old old
JSR old new new new new

Instructions that didn't make the cut

See also Synthetic instructions on NESDev Wiki.

Implied addressing

Mnemonic Description Approximate equivalent In other CPUs
SAX Swap A and X. PHX & TAX & PLA HuC6280 SAX
SAY Swap A and Y. PHY & TAY & PLA HuC6280 SAY
SXY Swap X and Y. PHX & PHY & PLX & PLY HuC6280 SXY
CLA Clear A. LDA #0 HuC6280 CLA
CLX Clear X. LDX #0 HuC6280 CLX
CLY Clear Y. LDY #0 HuC6280 CLY
ADZ Add carry to A. ADC #0
SBZ Subtract (1 − carry) from A. SBC #0
FLX Set N and Z flags (not C) according to X. INX & DEX
FLY Set N and Z flags (not C) according to Y. INY & DEY
TAS Transfer (copy) A to stack pointer. STX temp & TAX & TXS & LDX temp 65816 TCS
TSA Transfer (copy) stack pointer to A. STX temp & TSX & TXA & LDX temp 65816 TSC
TAP Transfer (copy) A to processor status. PHA & PLP
TPA Transfer (copy) processor status to A. PHP & PLA
RCC, RCS, REQ, RMI,
RNE, RPL, RVC, RVS		 Return from subroutine if condition. RCC is like BCS skip & RTS & skip: Z80 RET with condition

Non-implied addressing

Mnemonic Description Approximate equivalent In other CPUs
ADD Add memory or immediate to A without carry. CLC & ADC operand Z80, x86 ADD
SUB Subtract memory or immediate from A without carry. SEC & SBC operand Z80, x86 SUB
NEG Negate memory or A in two's complement. for accumulator: EOR #$FF & INC A Z80, x86 NEG
PSH Push memory or immediate to stack. STA temp & LDA operand & PHA & LDA temp x86 PUSH
PUL Pull (pop) from stack to memory. STA temp & PLA & STA operand & LDA temp x86 POP
BSR Branch to subroutine. like JSR but with PC-relative addressing HuC6280 BSR
JCC, JCS, JEQ, JMI,
JNE, JPL, JVC, JVS		 Jump if condition (see RCC etc. above). JCC target is like BCS skip & JMP target & skip: Z80 JP with condition
SCC, SCS, SEQ, SMI,
SNE, SPL, SVC, SVS		 Jump to subroutine if condition (see RCC etc. above). SCC sub is like BCS skip & JSR sub & skip: Z80 CALL with condition
TEB Exclusive-OR bits in memory according to A. TEB memory is like PHA & EOR memory & STA memory & PLA